Currently, the trend in integrated circuits is to more complex designs. For example, an integrated circuit may have previously included only a single core, such as processor circuit. Currently, integrated circuits are often designed with multiple cores having relatively complex interconnections. Thus, it is desirable to test integrated circuits during design and fabrication.
The IEEE 1149.1 JTAG recommendation provides a standard test architecture for use with integrated circuits. The JTAG recommendation provides that a core can be coupled with a test access port (TAP) controller used in testing various features of a core. As used herein, a core is a portion of an integrated circuit that can be tested using a controller. The core need not include a single processor or a particular set of circuits in an integrated circuit. Although JTAG provides a standardized test architecture, one of ordinary skill in the art will readily recognize that JTAG envisions a single core being tested by a single controller.
FIG. 1A depicts a conventional system 10 for testing an integrated circuit having multiple cores. Thus, multiple slave TAP controllers 20, 30, 40, and 50 as well as a conventional master TAP controller 60 are provided. The conventional slave TAP controllers 20, 30, 40, and 50 are cascaded. Consequently, data input to one conventional slave TAP controller 20, 30, and 40 can be cascaded to a subsequent conventional slave TAP controller 30, 40, and 50, respectively. Furthermore, each conventional slave TAP controller 20, 30, 40, and 50 is coupled to a core of an integrated circuit (not shown). Typically, the conventional master TAP controller 60 enables only one of the conventional slave TAP controllers 20, 30, 40, or 50 at a single time. Test data and instructions are transferred to the conventional slave TAP controller 20, 30, 40, or 50 that is enabled. When the transfer of data is complete, the conventional slave TAP controller 20, 30, 40, or 50 is disabled and the next conventional slave TAP controller is enabled. For example, suppose data is to be provided to the cores coupled to the conventional slave TAP controllers 20 and 30. Typically, the conventional slave TAP controller 20 is enabled. Test data is provided to the conventional slave TAP controller 20. The conventional slave TAP controller 20 is then disabled and the conventional slave TAP controller 30 is enabled. If the same test data is provided to both conventional slave TAP controllers 20 and 30, the test data is then cascaded from the conventional slave TAP controller 20 to the conventional slave TAP controller 30. If different test data is provided to the conventional slave TAP controller 30, then the new test data is input directly to the conventional slave TAP controller 30. In some conventional systems 10, the conventional master TAP controller 60 does allow for more than one of the conventional TAP controllers 20, 30, 40, and 50 to be enabled simultaneously. However, test data is still apparently cascaded between the conventional slave TAP controllers 20, 30, 40, and 50. Thus, in the example above, the time taken to serially disable the conventional slave TAP controller 20 and enable the next conventional slave TAP controller 30 is saved. However, the latency in receiving the test data still differs for different TAP controllers because the data is cascaded or received serially. Thus, testing may be slower.
Accordingly, what is needed is a system and method for more rapidly testing integrated circuits. The present invention addresses such a need.